Hardware

Hardware security and trust for wireless integrated circuits

Prof. Haralampos Stratigopoulos, Sorbonne Université

-

B2 5220

Abstract We will discuss Integrated Circuit (IC) security and trust threats and corresponding countermeasures with a focus on wireless ICs. We will present solutions to protect RF transceiver ICs against piracy attempted by malicious System-on-Chip (SoC) integrators, foundries, or end-users via reverse-engineering. We will also present hardware Trojan attacks on RF transceivers aiming at creating a covert channel for stealing sensitive information, i.e., cypher keys. Brief Biography Haralampos-G. Stratigopoulos received the Diploma in electrical and computer engineering from the National

Efficient Machine Learning across Hardware, Software, and Algorithms

-

B2 L5 R5209

Deep neural networks (DNNs) are revolutionizing computing, necessitating an integrated approach across the computing stack to optimize efficiency. In this talk, I will explore the frontier of DNN optimization, spanning algorithms, software, and hardware. We'll start with hardware-aware neural architecture search, demonstrating how tailoring DNN architectures to specific hardware can drastically enhance performance.

Hardware Realization of Chaos Based Block Cipher for Image Encryption

1 min read ·
Mohamed L. Barakat, et al., "Hardware realization of chaos based block cipher for image encryption." In ICM 2011 Proceeding, 2011, 1. Unlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be

Yuxiang Liu

PhD candidate in the Networking Research Lab(NETLAB) at King Abdullah University of Science and Technology.